1. Field of the Invention
This invention also relates to a new type of extremely low noise Phase/Frequency Discriminators/Detectors (PFD) providing significant advantages over prior art in frequency acquisition, phase locking/tracking and other applications, as well as FM demodulators employed in techniques for phase noise improvements of oscillators and other signals and sources and in highly linear FM modulators.
2. Background of the Related Art
Communication and other electronics systems use internally generated signals for various functions. Such signals are often generated by local oscillator sources for purposes of signal frequency up or down conversion, modulation/demodulation, as well as for various clock signals used by processors and controllers. It is often required that these signals have high spectral purity and low phase noise. Low phase noise is particularly important in communication systems using phase or frequency modulation schemes such as quadrature amplitude modulation (QAM) (which is used in digital cable TV and high speed data modems), quadrature phase modulation (QPSK) (which is used in digital cellular telephony), FM modulation (which is used in analog cellular telephony), and other similar modulation formats employed in other communication systems.
It is well known in the art that frequency synthesizers play a key role in generation of such high quality signals. It is also well known that a frequency discriminator (or frequency comparator) is an integral part of frequency synthesizers. A general discussion of phase lock loop (PLL) based frequency synthesizers is found in aforementioned commonly assigned U.S. patent application Ser. No. 09/580,513 entitled “Rational Frequency Synthesizers” which is incorporated herein in its entirety by this reference. As discussed therein, to achieve low phase noise, it is important to operate the synthesizer at high comparison frequencies. The comparison frequency in PLLs is the frequency at which the comparison (or detection) of the phase and frequency of the scaled versions of both the oscillator and reference signals actually occurs. The undesired noise originating in dividers and phase detector will be multiplied by the loop by a factor equal to the total division ratio in the loop. The multiplied noise will then phase modulate the voltage controlled oscillator (VCO) and will significantly degrade and limit its phase noise performance. This noise multiplication is often the key factor causing degradation of phase noise performance in synthesizers. Thus, to achieve low phase noise performance, it is important to keep the multiplication factor low, i.e., the comparison frequency high.
In a PLL frequency synthesizer, a frequency lock must occur before a phase lock can occur. During acquisition of the phase lock, the phase detector (PD) alone may not be able to provide an adequate steering signal necessary for locking, and additional means for assisting the frequency acquisition is often necessary. For the purpose of assisting, or enabling acquisition, various means are utilized, such as a frequency discriminator (FD) also called frequency detector, or other means such as frequency pre-tuning or frequency sweeping. In the acquisition process, the FD (or one of the aforementioned other means) provides a DC steering signal of the right polarity, consistent with the sense of the frequency difference which guides the oscillator in the right direction towards a frequency lock, or at least until the frequency falls inside the capture range of the PD. Thereafter, the PD is once again relied upon to keep the PLL phase-locked. As part of a negative feedback loop, the FD must provide a high (e.g., positive) voltage when the frequency at one input is higher than the other and a low (e.g., zero) voltage when the frequency at that input is lower than the other.
Among all methods used to perform this function the FD is by far the most commonly used means for frequency acquisition in PLL frequency synthesizers. The frequency discriminators of the prior art used in frequency synthesizers are inherently limited in speed. They utilize flip-flops with their reset line being fed back from the output, as illustrated in FIGS. 6A and 6B. The relatively long propagation delays and settling times of the flip-flops limit the maximum speed (or frequency) of the FD operation, and thus indirectly limits the maximum comparison frequency in a PLL employing such an FD.
FIGS. 6A and 6B show typical circuits used in the industry, which accomplish a combined PD and FD function, being the phase-frequency detection (PFD). They are the Dual-D and the Quad-D Flip-Flop PFDs respectively. These circuits are implemented with conventional logic, and often found in digital bi-polar or CMOS integrated circuits. The outputs of these PFDs need to drive a charge pump operating in conjunction with an external LPF or integrator. The charge pump (not shown in the figures) typically consists of a voltage-controlled current source that outputs either a positive or a negative current depending on the value of the control voltages (UP and DN lines). When UP and DN are equal the output current should be zero. When the frequency of one input is different from the other, the UP or the DN lines engage to pull the VCO frequency in the desired direction.
The limitations of these flip-flop based circuits are mainly related to speed (i.e., to the maximum operating frequency). Their physical limitations are the set-up and hold times of the flip flops, the propagation delays from their Clock, Reset and D inputs to the outputs, as well as the usual propagation delays of the combinatorial logic and their interconnections. Those limitations produce two types of artifacts associated particularly with the phase-detection, namely the “dead-zone” and the “blind-spot”. The “dead zone” is the region where the phases of the two input signals (F.sub.ref and F.sub.in) produce a close to zero error that goes undetected. The phase range of the dead zone is in the order of the phase delay caused by one or two units of propagation delays of the gates. To minimize this effect it would be necessary to reduce the compared frequencies until the phase error associated with this zone becomes insignificant. The “blind-spot” is the region where the phase difference approaches plus or minus 3600, in which the edges of every next cycle occurs during the resetting pulse to the PD flip-flops. This imposes the same type of speed limitations as the “dead zone”. In a typical CMOS integrated circuit having typical gate and flip-flop delays of few nano-seconds and gate delays of few hundred pico-seconds, the maximum workable frequency might be well below 30 MHz for the phase-detection and not more than 60 MHz for the frequency discriminator.
Another disadvantage of performing phase detection using one of those PFDs is that they are quite noisy, and require a charge pump with a relatively narrow low-pass filter (or integrator) because the phase correction pulses to the charge pump may occur at very low frequencies. The frequency detection, although somewhat better in the Quad-D topology of FIG. 6B than that of the Dual-D of FIG. 6A, suffers from the same speed limitations as the phase detection. Scaling the input frequencies prior to the PFD would lessen the speed constraints. For example using a divider by N prior to both the F.sub.ref and F.sub.in inputs would make the PFD operate at 1/N times the frequency. While the FD function of the PFD would not suffer significantly by this scaling, the PD function would: operation at one Nth of the frequency would increase the PLL phase noise power contribution significantly as discussed earlier by increasing the total division ratio in the loop (usually between a factor of N and N.sup.2). If the PLL phase noise is of the essence for a given design, then the PD needs to be capable of operating at higher comparison frequencies, so that N would be minimal. One such circuit would be a simple logic exclusive-OR gate, also known as XOR. Since this type of phase detector cannot perform the FD function, this function would need to be implemented separately.
Another disadvantage of the prior art FDs is that their gain (expressed in Volts/Hz) is low, and cannot be controlled. It can be seen from the transfer function outlined in FIG. 6C that when F.sub.ref and F.sub.in are within an octave of each other the gain is at its highest but it is still limited to Vcc/F.sub.ref. The consequence is that when F.sub.ref and F.sub.in are very close to each other (i.e., close to lock condition) the steering voltage output (around ½ Vcc) would be extremely small, potentially slowing down the acquisition speed.
It should be noted that frequency discrimination is very similar to frequency demodulation. The frequency discriminator in synthesizer applications compares a frequency of interest to a reference frequency and produces a difference, or error signal. This signal must have the right polarity (sign), but does not need to be linearly proportional to the frequency difference of the two frequencies. For example, the error signal can be a bi-level signal, where one level corresponds to negative difference and the other to positive difference of the two frequencies, effectively providing a frequency comparator function. An FM demodulator, on the other hand, also needs to produce the difference (error) signal, but this time the error signal must be linearly proportional to the frequency difference. Increasing the demodulator gain to an extreme, the proportional signal can approach the bi-level signal. Further, a discriminator must operate down to DC frequency (DC coupled), while a demodulator may not have to operate down to DC, but often only down to some low frequency (AC coupled demodulator). In summary, a frequency discriminator can be viewed as a special case of a demodulator, i.e., as a high gain, DC coupled FM demodulator.
To provide better insight into the operation of frequency demodulators and discriminators of the present art, the analytical background of FM modulation and demodulation is reviewed below.
A Frequency Modulated (FM) waveform can be expressed as:FM(t)=cos [.omega..sub.ct+.phi.(t)]  (1)
where:
.omega..sub.c—FM carrier frequency
.phi.(t)=k.sub.v.intg.m(t)dt—instantaneous phase (or angle, argument) of the waveform
.phi.′(t)=k.sub.vm(t)=.delta..omega.(t)—instantaneous frequency deviation
m(t)—modulation signal, i.e., base band (BB) information
k.sub.v—constant of proportionality in the FM modulator
i.e., in FM modulation, instantaneous frequency deviation .delta..omega.(t) of the carrier is proportional to the modulation signal m(t), while the instantaneous phase .phi.(t) is a time integral of the instantaneous frequency deviation .delta..omega.(t).
Because the argument .phi.(t) of the FM waveform represents a time integral of the modulation signal m(t), it follows that demodulation of an FM signal is a reverse process, where a derivative of the FM argument with respect to time contains the demodulated information:1 BB(t)=k′(t)=kt[(t)]=kt[kvm(t)t]=kkvm(t)   (2)
where BB(t) is a demodulated FM baseband signal, equal (within a constant k.multidot.k.sub.v) to the modulation signal m(t); k is a constant of proportionality in the demodulator and k.sub.v is a constant of proportionality in the modulator.
From equation (2) it follows that in order to demodulate an FM waveform, a demodulator must involve the operation of differentiating the argument of the FM waveform with respect to time. Different types of FM demodulators differ from each other in the manner in which this function is accomplished. In general, the differentiation of the argument of FM waveform can be accomplished by hardware, by digitization & computation (i.e., by Digital Signal Processing—DSP) or by the combination of the two.
In the computational approach, instantaneous samples of the argument of the FM signal are obtained (at a sampling rate equal or higher than the Nyquist rate), the samples are digitized and the time derivative is computed, yielding demodulated information. This approach is limited to lower FM carrier frequencies, where the limitation is imposed by analog to digital converters (ADC) speed, as well as by the computational speed. The ADC speed limitation problem can be overcome to some extent by “undersampling” (i.e., where the sampling rate is lower than the FM carrier frequency, but higher than twice the maximum modulation frequency). In a combined approach, the FM signal can be down-converted to lower frequencies, or to zero intermediate frequency (IF), and then sampled and computationally processed.
The hardware approach to differentiating the argument of the FM waveform usually involves an approximation of this operation, implemented in hardware. Most hardware methods utilize, in one form or another, a mathematical approximation described below:
Starting with a definition of a first derivative of a function:2′(t)=(t)t=(t)−(t−t)t   (3)
and multiplying eq. (3) by dt, the following expression is obtained:.phi.(t)−.phi.(t−dt)=.phi.′(t)−dt   (4)
The dt is infinitesimally small increment of time. It can be approximated with a finite value of time, for example with a finite time delay .tau., provided that this time delay is small compared with the maximum rate of change of signal .phi.(t), i.e. .tau.<<1/f max, where f max is the highest frequency in the baseband modulation signal.
Approximating dt.apprxeq..tau. in equation (4):.phi.(t)−.phi.(t−.tau.).congruent..tau..multidot..phi.′(t)   (5)
From equation (2), substituting k=.tau., it directly follows that eq. (5) represents a demodulated baseband signal:BB(t)=.tau..phi.′(t)=.phi.(t)−.phi.(t−.tau.)=k.multidot.k.sub.v.multidot.m−(t)   (6)
Equation (6) summarizes the outcome of the above approximate differentiation process. It states that the demodulated baseband signal can be obtained by finding a difference of the instantaneous phase of the FM waveform in the point of time t and in a delayed point of time t.−tau..
To determine how small a time delay .tau. needs to be in respect to maximum frequency of the modulation signal f max, a Laplace transform of equation (5) can be used. Applying the Laplace transform to the left hand side of eq. (5) yields:L[.phi.(t)−.phi.(t−.tau.)]=L[.phi.(t)]−L[.phi.(t−.tau.)]=.PHI.(s)−.PHI.(s)−.multidot.e.sup.−.tau.s=.PHI.(s)(1−e.sup.−.tau.s)   (7)
where .PHI.(s) is a Laplace transform of .phi.(t) and s is a complex frequency variable s=.sigma.+j.omega..
Approximating e.sup.−.tau.s with a Taylor expansion around zero:3−s1−s+(s)22   (8)
From eq. (8):41−−ss−(s)22=(1−s2)s   (9)
and substituting eq. (9) in eq. (7):5 L[(t)−(t−)](1−s2)s(s)   (10)
Eq. (10) represents the Laplace transform of the left-hand side of eq. (5). Comparing this equation with the Laplace transform of the right hand side of eq. (5):L[.tau..phi.(t)′]=.tau.s.PHI.(s)   (11)
it follows that the two sides of eq. (5) are equal, provided that6 s21   (12)
This term represents the error (or distortion) caused by the approximation dt.apprxeq..tau.. For instance, if s=.omega..sub.max (highest modulation frequency), and allowing for 1% (0.01) distortion in the demodulated signal, the maximum acceptable delay can be computed from eq. (13):7 max 2 0.01 0.02 max=0.02 2 f max=0.01 f max   (13)
Audio FM demodulator example:f max=20 kHz and from eq. (13) it follows that the maximum acceptable delay for 1% distortion is:8 max 0.01 20 kHz=0.16 s   (13a)
A widely used hardware implementation utilizing time delay per the concept above is a well known quadrature FM demodulator of the related art, illustrated in FIG. 1. The modulated FM signal 10 is split two ways, one passed without delay and the other passed through a delay circuit 2 having a delay .tau. The phase shift of the delayed arm is adjusted for 90.degree. at FM carrier center frequency. The relative phases of the two arms are then compared in a phase comparator or phase detector 4, at the output of which, after passing through low-pass filter 6, demodulated baseband signal BB(t) is obtained.
The output 8 of the demodulator of FIG. 1, considering fundamental frequency terms only, can be expressed as:BB(t)=FM(t).multidot.FM(t−.tau.)=cos [.omega..sub.ct+.phi.(t)].multidot.cos−[.omega..sub.c(t−.tau.)+.phi.(t−.tau.)]  (14)
Using a trigonometric identity for product of two cosines:9 cos A cos B=12 cos(A−B)+12 cos(A+B)   (15)
and applying identity (15) to equation (14):10 BB(t)=12 cos [(t)−(t−)+c]+12 cos [2 ct−c+(t)+(t−)]  (16)
The low pass filter (LPF) 6 at the output of the mixer removes the sum frequency and all higher frequency terms, and for .omega..sub.c.tau.=−90.degree. (or odd multiples of 90.degree.) at the carrier frequency .omega..sub.c, the output is:11 BB(t)=12 cos [(t)−(t)−90.degree.]=12 sin [(t)−(t−)]  (17)
Substituting .phi.(t)−.phi.(t−.tau.) with .tau..phi.′(t) from eq. (5):12 BB(t)12 sin [′(t)]  (18)
and substituting .phi.′(t)=k.sub.vm(t) from eq. (1):13 BB(t)12 sin [kvm(t)]  (19)
Using small angle approximation of sine function:sin x.congruent.x for small x (x<<1 radian):   (20)
Applying approximation (20) to equation (19):14 BB(t)12 kvm(t)—Demodulatedsignalatoutput8   (21)
Equation (21) represents a demodulated signal in the FM demodulator of the related art. In this type of demodulator, delay .tau. is obtained with a tuned circuit (either with single or double tuned LC circuit, or with ceramic resonators). The delay must be small enough to achieve low distortion, per eq. (13). Furthermore, the delay must also produce a quadrature phase shift (90.degree.) at the center frequency .omega..sub.c (if the phase delay is not exactly 90.degree., the demod would still work, but at reduced performance).
The specific requirement for phase quadrature imposes a practical limit for the use of this demod to a fixed frequency. At that fixed center carrier frequency, the circuit is adjusted for a precise 90.degree. phase shift. An application example of this type of demod at fixed frequency is in FM stereo receivers. They use an IF frequency of 10.7 MHz, where a fixed tuned circuit (either a single tuned LC circuit, or a double tuned LC circuit with coupled coils) is used to obtain 900 phase shift at that frequency.
The problem of using this type of demodulator in frequency agile applications comes from the difficulty in achieving flat group delay and maintaining a 90.degree. phase shift over broader range of carrier frequencies .omega..sub.c. Furthermore, this solution is not suitable for integration into integrated circuits (ICs), due to difficulties in implementing a required time delay and phase shift inside the integrated circuit.
Frequency agility has been resolved in another type of demodulator of the prior art, shown in FIG. 2. Instead of splitting and delaying the FM signal before the phase detector, as in the demodulator of FIG. 1, the FM signal 12 is first down-converted to zero IF frequency and then delayed, prior to phase comparison. In this type of demodulator, the FM signal 12 with carrier frequency (.degree. c is split in two in-phase signals 14 and 16, and each signal is down-converted to zero IF frequency by mixing it with local oscillator (LO) 26 of frequency .omega..sub.0. One of the in-phase signals (14) is mixed with zero phase LO signal 32 in mixer 18, producing the in-phase (I) output 22, while the other in-phase signal (16) is mixed with quadrature phase (−90.degree.) LO signal 30 in mixer 20, producing quadrature (Q) output 24. The mixing process produces two sidebands—the lower sideband (LSB) having the difference frequency .omega..sub.c−.omega..sub.0 and the upper sideband (USB) having the sum frequency .omega..sub.c+.omega..sub.0, i.e., this mixing results in a double sideband (DSB) conversion. Each of the I and Q arms at the output of respective mixers contains DSB signals: the sum of the LSB and the USB components, as shown in FIG. 2, where the sign “−” designates the LSB sideband (I.sup.− or Q.sup.−) and “+” designates the USB sideband (I.sup.+ or Q.sup.+).
For further processing, it is necessary to remove the undesired USB components from both arms. The low pass filter (LPF) 34 in I arm and LPF 36 in Q arm are used to accomplish this task: the upper sidebands are filtered out and desired lower sidebands I.sup.− (38) and Q.sup.− (40) at difference frequency .omega..sub.c−.omega..sub.0 are extracted. Both I arm 38 and Q arm 40 at the output of LPF filters are split two ways, one way delayed by .tau. (in delay circuit 42 for 1 arm and in 44 for Q arm) and the other way not delayed. Next, the cross-mixing of two pairs of signals follows (38 and 48 in mixer 52. and 40 and 46 in mixer 50). The summation, with the proper sign in the summing circuit 58 of the products 54 and 56 thereof is conducted, yielding baseband output 60 per equations below:BB(t)=I.sup.−(t−.tau.).multidot.Q.sup.−(t)−I.sup.−(t).multidot.Q.sup.−(t−.−tau.)   (22)
By substituting individual terms with respective trigonometric expressions and expanding eq. (22), it can be shown that the BB signal 60 at the output of FIG. 2 is equal to:15 BB(t)=14 sin [(c−o)+(t)−(t−)]  (23)
The LO frequency .omega..sub.0 does not need to be equal (or phase locked) to the FM carrier frequency .omega..sub.x; however, it needs to be close enough, so that the difference frequency .omega..sub.c−.omega..sub.0 is around zero (zero IF) and all modulation sidebands fall within the pass-band of the LPF filter. Conversely, the LPF bandwidth needs to be high enough to pass the highest frequency of interest. In eq. (23) it is necessary to keep the argument small in order to achieve linear demodulation, in accordance with the to small angle approximation of sin x.congruent.x in eq. (20). This condition is met for (.omega..sub.c−.omega..sub.0).tau..congruent.0, i.e. .omega..sub.0.congruent..omega..sub.c. Using equations (17) through (20), the demodulated signal 60 at the output of FIG. 2 can be expressed with the following equation:16 BB(t) 14kvm(t)   (24)
which is identical to eq. (21), except for a reduced level (by a factor of two).
While the solution of FIG. 2 resolves the frequency agility issue, it is still not suitable for integration into integrated circuits (ICs), due to difficulties in implementing low pass filters inside the ICs. Thus, external filters would have to be used, which would require a signal to exit the IC for external filtering, pass through a filter (the signal will at this point become an analog signal) and in the case of digital Ics, re-entry into the IC will be required through some type of a comparator that will convert the analog signal back to digital.
Also, the performance of the prior art circuit directly depends on the phase and amplitude balance of the LPFs 34 and 36 in the I and Q arms. Any amplitude and/or phase imbalance in the two paths 38 and 40 will cause degradation of the quality of the demodulated signal (i.e., the noise and distortion performance will degrade). This places additional burden on low pass filter design and implementation for the prior art.
Thus, considering the limitations of both frequency discrimination and frequency demodulation of the prior art, those of skill in the art will recognize the need for 1) an alternative solution for frequency discrimination, one that can operate at much higher comparison frequencies for application to frequency synthesizers, thereby substantially improving phase noise performance, and 2) an alternative solution for demodulation for application to FM demodulation, one that facilitates frequency agile operation, is simple in design and suitable for implementation in integrated circuits.